1. Field of the Invention
This invention relates to transistors and more specifically to a high density trenched DMOS transistor.
2. Description of the Prior Art
DMOS (diffused metal oxide semiconductor) transistors are well known. Typically these transistors are used in integrated circuits or for power transistors. Some DMOS transistors are trenched transistors; a conductive gate electrode, typically polycrystalline silicon (polysilicon), is located in a trench in the transistor substrate, and the sidewalls and bottom of the trench are insulated with silicon dioxide. The trenched structure increases transistor density by reducing the chip surface area consumed by the polysilicon gate of each transistor. Typically such transistors are used in low to medium voltage applications, and each transistor includes a large number (thousands) of cells. Each cell is defined by a source region diffused into the substrate and by the gate electrode trenches.
The provision of the trenches advantageously increases cell density and also reduces the undesirable parasitic JFET (junction field effect transistor) resistance which typically is present between adjacent cells. The parasitic JFET resistance is one component of the total on-state resistance, R.sub.DSON, which is characteristic of such transistors in their conductive (on) state; it is desirable to minimize the on-resistance.
However, trenches do not completely eliminate parasitic JFET resistance. When cell density is high in a trenched DMOS transistor, a new parasitic JFET phenomenon gradually appears between the adjacent deep body P+ regions which extend alongside the trench and are typically used to protect the trench regions and ensure reliability. Unfortunately, this new JFET resistance becomes a significant component of on-resistance as cell density increases.
By design, avalanche breakdown occurs in the P+ doped regions away from the trench bottom. In a typical DMOS transistor having a trenched gate electrode, in order to avoid destructive breakdown occurring at the bottom of the trench into the underlying drain region, the deep body P+ region extends deeper than does the bottom of the trench. Rather than the destructive breakdown occurring at the trench bottom, therefore instead the avalanche breakdown occurs from the lowest portion of this deep body P+ region into the underlying relatively nearby drain region.
It is well known that the trenched DMOS transistor structure is superior to a planar DMOS transistor in terms of drain-source specific on-resistance, which is resistance times the cross-sectional area of the substrate carrying the current. The JFET resistance, inherent in planar DMOS transistors, is significantly reduced and cell density is enhanced by reducing the length of the gate electrode.
An example of a planar DMOS transistor is disclosed in Lidow et al. U.S. Pat. No. 4,642,666 issued Feb. 10, 1987 which discloses as shown in present FIG. 1 (similar to FIG. 2 of Lidow et al.) a high power MOSFET in which two laterally spaced sources each supply current through respective channels in one surface of a semiconductor chip, controlled by the same gate. The epitaxially deposited semiconductor material immediately adjacent and beneath the gate and in the path from the sources to the drain is of relatively high conductivity (is highly doped), thereby substantially reducing the on-resistance of the device without affecting the device breakdown voltage.
Thus as shown in present FIG. 1, the Lidow et is al. MOSFET is formed in a chip of monocrystalline silicon 20. Two source electrodes 22 and 23 are separated by a metallized gate electrode 24 which is fixed to but spaced apart from the semiconductor device surface by a silicon dioxide layer 25. Each of source electrodes 22 and 23 supply current to a drain electrode 26 which is fixed to the bottom of the wafer. An N- doped epitaxial layer is deposited on N+doped substrate 20. P+ doped regions 30 and 31 each include a curved lower portion which serves as a deep body region. Two N+ regions 32 and 33 are formed at the source electrodes 22 and 23 respectively and define, with the P doped regions 34 and 35, channel regions 36 and 37 which are disposed beneath the gate oxide 25 and can be inverted from P-type to N-type by the appropriate application of a bias voltage to the gate 24 in order to permit conduction from the source electrodes 22 and 23 through the inversion layers into the central region disposed beneath the gate 24 and then to the drain electrode 26. (Reference numbers used herein referring to FIG. 1 differ somewhat from those in the Lidow et al. disclosure.)
In the central region beneath the gate 24 is located a highly conductive N+ doped region 40 disposed immediately beneath the gate oxide 25. The N+ region has a depth of about 4 .mu.m. Region 40 is relatively highly doped compared to the N- doped region immediately beneath it. By making region 40 of relatively highly conductive N+ material by a diffusion or other operation, the device characteristics are significantly improved and the forward on-resistance of the device is reduced by a factor greater than two. Provision of the high conductivity region 40 does not interfere with the reverse voltage characteristics of the device. Accordingly the forward on-resistance of the ultimate high power switching device is significantly reduced.
However the Lidow et al. device is a planar (non-trenched) transistor structure and has the accompanying drawbacks of relatively low cell density and relatively high inherent JFET resistance.